Timed Pulse

Behavior

Timed Pulse generates pulses at a fixed, predictable rate, regardless of the frequency of the underlying clock. Each output pulse is one clock cycle wide by default. In other words, the output is 1 for one full clock cycle, then the output is 0 for as many clock cycles as needed before th enext pulse to achieve the desired rate. The output of Timed Pules can be useful as an enable signal for registers, counters, and other components that should update at some fixed rate that is slower than the system clock rate.

In the example above, the Timed Pulse component is configured to generate one full-cycle pulse at a 1Hz rate, which it achieves even though the clock is ticking much faster than 1Hz. The Timed Pulse output is then used to drive a blinking LED, which flashes briefly once each second. It also enables a counter, which counts up steadily once per second.

Note: The underlying clock driving the Timed Pulse must be at least as faast as the desired target pulse rate, and depending on the frequency of the underlying clock, the actual pulse rate achieved in practice may only approximate the desired target pulse rate. A faster underlying clock will allow a more accurate pulse rate. If the system clock is close to the desired pulse rate, pulses can sometimes occur back-to-back, in consecutive clock cycles, if that's needed to achieve the desired target pulse rate. In the limit, when the system clock is equal to the desired pulse rate, then a pulse will occur in every clock cycle, meaning the output of Timed Pulse will be, in effect, a constant 1.

Ports

There is one output pin, on the east edge, carrying the pulse signal. There is one input pin on the south edge, which should be connected to a clock that is faster than the desired target pulse rate.

Keyboard Shortcuts

When using Edit Tool:

Arrow keys while holding the option key (⌥) or Alt key change the Label Location property.

Properties

Interval

Sets the desired target pulse rate. Must be positive.

Unit

Determines how Interval is interpreted, either: seconds, milliseconds, microseconds, nanoseconds, Hz, kHz, or MHz.

Trigger

Determines the width and alignment of output pulses with the underlying clock.

Rising Edge: Each pulse starts on a rising clock edge and ends on the next rising clock edge.
Falling Edge: Each pulse starts on a falling clock edge and ends on the next falling clock edge.
High Level: Each pulse coincides with the high portion of the clock cycle.
Low Level: Each pulse coincides with the low portion of the clock cycle.

Label

Text to show next to the component.

Label Location

Location of the label relative to the component.

Label Font

Font for the label.

Label Color

Color for the label.

Poke Tool Behavior

Timed Pulse does not respond to pokes.

FPGA Synthesis

Supports VHDL and Verilog synthesis.