Transmission Gate

Library:	Analog
Introduced:	2.7.0 (moved to Analog in 4.0.2 HC)
Appearance:

Behavior

A transmission gate has three inputs, called source, n-gate, and p-gate; and it has one output, called drain. When diagrammed, the source input and drain output are drawn connected by two plates; Logisim draws an arrowhead to indicate the direction of flow from input to output. The two gate inputs are drawn as lines connected to plates parallel to each of the plates connecting source to drain. The p-gate input's line has a circle, while the n-gate input's line does not.

	p-gate
source		drain
	n-gate

The transmission gate is essentially just the combination of two complementary transistors connected in parallel. Indeed, a similar behavior can be achieved in Logisim by using a pair of transistors. However,

The values at n-gate and p-gate are expected to be opposite to each other. If p-gate is 0 while n-gate is 1, then the value found at source is transmitted to drain. If p-gate is 1 while p-gate is 0, then the connection is broken, so the value at drain is left floating ('X'). In all other cases, drain receives an error ('E') output — unless source is floating ('X'), in which case drain is floating as well. This behavior is summarized by the following table.

p-gate	n-gate	drain
0	0	E*
0	1	source
1	0	X
1	1	E*
E/X	any	E*
any	E/X	E*

* Note: If source is X, drain is X; otherwise drain is E.

If the Data Bits property is more than 1, each gate input is still a single bit, but the gate values are applied simultaneously to each of the source input's bits.

Note: Logisim's transmission gate is not bidirectional: values can only flow from source to drain. This is in contrast to typical transmission gates which can operate in either direction. Moreover, in Logisim, if the transmission gate's two control signals are not complementary, then the gate will simply output an error in most cases, whereas actual transmission gates would likely pass current in on direction or the other in some scenarios.

Pins (assuming component faces east, gate line top/left)

West edge (input, bit width matches Data Bits property): The component's source input that will transmit to the output if triggered by the p-gate and n-gate inputs.
North edge (input, bit width 1): The component's p-gate input.
South edge (input, bit width 1): The component's n-gate input.
East edge (output, bit width matches Data Bits property): The component's output, which will match the source input if p-gate is 0 and n-gate is 1, or it will be floating if p-gate is 1 and n-gate is 0. For all other values on p-gate and n-gate, the output is an error value or, in some cases, a floating value.

Properties

When the component is selected or being added, Alt-0 through Alt-9 alter its Data Bits property and the arrow keys alter its Facing property.

Facing: The direction of the component (its output relative to its input).
Gate Location: The location of the gate input.
Data Bits: The bit width of the component's inputs and outputs.

Poke Tool Behavior

None.

FPGA Synthesis

None. FPGA devices generally do not support tri-state devices.

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