PCM Sink

Library:	Audio
Introduced:	5.0.3-HC
Appearance:

Behavior

PCM Sink converts digital PCM data provided by a circuit, in real-time, into an analog audio signal for playback using the native audio system. It includes an internal data buffer to account for slight variations in Logisim's simulation speed or slight mismatches between the simulation tick rate and the intended audio playback rate. The PCM Sink component has a data input on the west edge, a write-enable input on the south edge, and a clock input on the south edge. When the write-enable input is 1 and the clock is triggered, one new data value is captured at the data input and added to the playback buffer. At all times, whenever the playback buffer is not empty, the audio data in the buffer is removed from the buffer at a steady rate, converted to analog audio, and played through the speakers or other system audio output. If the playback buffer is full, new data is ignored.

The amount of data in the playback buffer, as a fraction of the buffer's total capacity, is shown as an overlay on the PCM Sink component, with the gray bar indicating pending data to be played and the white color indicating empty space in the buffer for more data. A blue speaker icon indicates that data is being converted and played as audio. When the buffer is empty or overflows, when the clock is stopped, or if there are any errors in playback, the speaker icon will show as red.

Simulation Tick Rate: Because audio data must be feed to the the sound system at a fixed rate, you must set Logisim's simulation clock tick rate and the PCM Sink's Sample Rate property to match. If the simulation tick rate runs faster than the PCM audio Sample Rate, the playback buffer will overflow and audible glitches will be heard. If the simulation runs slower than the PCM audio Sample Rate, the playback buffer will nearly always be empty, resulting in little or no audio produced.

Pins

West edge (input, bit width matches Data Bits property)

Sample: When the clock triggers, the value found at this input is copied into the the real-time audio playback buffer. If the value contains undefined or error bits, the entire sample value is discarded.

South edge, left side (input, bit width 1)

Write Enable: When this value is 1, clock triggers and audio data sampling and playback is enabled. When the value is 0, the Sample and Clock inputs are ignored.

South edge, right pin marked with triangle (input, bit width 1)

Clock: At the instant that this is triggered as specified by the Trigger property, the component adds the Sample input value, if it is fully defined and not an error value, to the playback buffer for conversion and audio playback.

Properties

When the component is selected or being added, Alt-0 through Alt-9 alter its Data Bits property.

Trigger

Configures how the clock input is interpreted. The value rising edge indicates that the register should update its value at the instant when the clock rises from 0 to 1. The falling edge value indicates that it should update at the instant the clock falls from 1 to 0.

Sample Rate

The rate at which the audio playback system will be configured. Logisim's tick rate should be configured to match this value.

Data Bits

The bit width of the Sample value.

Numeric Type

The format for the Sample value, either signed twos complement or unsigned.

Buffer Capacity

The capacity, in number of samples, of the audio playback system. This provides buffering to account for differences between the audio playback rate, defined by the Sample Rate property, and Logisim's simulation tick rate, which can vary unpredictably depending on many factors. However, larger buffer capacity can also result in higher latency, a lag between when data is captured from the Sample pin and when it is played back as audio.

Poke Tool Behavior

None.

FPGA Synthesis

Not yet supported.

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