RAM

Library:	Memory
Introduced:	2.0 Beta 1
Appearance:	Separate Data Buses Bidirectional Data bus Classic Logisim: ANSI:

Behavior

The RAM component, easily the most complex component in Logisim's built-in libraries, stores up to 16,777,216 values (specified in the Address Bit Width property), each of which can include up to to 32 bits (specified in the Data Bit Width property). The circuit can load and store values in RAM, either one at a time, in pairs, or four at a time. Also, the user can modify individual values interactively via the Poke Tool, or the user can edit, export, or import the contents via the Menu Tool.

Current values are displayed in the component. Addresses are shown in hex to the left of the display area, and memory contents are shown in hex inside the display area. The value at the currently selected address is displayed with a dark highlight and white text.

The RAM component supports two different interfaces, depending on the Databus implementation property.

One bidirectional data bus

The component includes a single port on its east side that serves for both loading and storing data. Which operation is performed—loading or storing—depends on the inputs labeled L and S: L=1 (or floating) indicates to load (from RAM to the data bus) the data at the address designated on the component's west side, and S=1 indicates to store (from the data bus to RAM) the data given on the port into the given address. To transmit data into and out of the component in both directions on a single bus wire, you will need to use a Tri-State Buffer, as illustrated in the example below, or other components that support floating outputs (e.g. components that have an 'Output Value' property with support for floating outputs).

Separate data bus for read and write

Two data ports are provided—one input data port on the west side for storing data into RAM, and a separate output port on the east side for loading data from RAM. This style of data interface removes the necessity of dealing with the Tri-State Buffers and so it generally easier to use. With this interface, the output port will always be enabled, and there is no L control port: effectively, the RAM will load values to the output databus on every cycle. The S control port controls whether data is stored.

Single, Dual, and Quad Lines Modes

Logisim RAM has a 'Line Size' property that controls how many locations ("lines") of memory are accessed at a time. Setting 'Line Size' to 'Single' is the simplest case: at most one location is accessed during each clock cycle, and there is one databus labeled D (either a single bidirectional port, or a pair of one input and one output port both labeled D). When 'Line Size' is set to 'Dual', however, the RAM component can read or write up to two locations simultaneously, and there are two databuses (either two bidirectional ports, or two pairs of unidirectional ports), labeled D and 1. In 'Quad' mode, RAM will read or write up to four locations, with four databuses labeled D, 1, 2, and 3. The addresses accessed are all consective: for 'Dual' line mode, RAM will access addresses A and A+1; for 'Quad' line mode, RAM will access addresses A, A+1, A+2, and A+3.

In 'Single' line mode, the single input S controls whether a store operation is performed for the given address. In 'Dual' and 'Quad' line modes, there are additional inputs to control which bytes (if any) are stored during a store operation. For example, in 'Quad' mode, there are control signals labeled S0, S1, S2, and S3, which control whether a store is performed for addresses addresses A, A+1, A+2, and A+3, respectively.

Address Alignment

In 'Dual' and 'Quad' line modes, the selected address must be aligned to a multiple of 2 or 4, respectively. There is no support for mis-aligned accesses. This means the lowest bit or lowest two bits of the address must always be zero in those modes. If the address is mis-aligned, RAM will not store data, and it will output all error (E) values instead of loading data from the RAM contents.

The decision to omit support in Logisim for mis-aligned addresses is deliberate. Support for mis-aligned addresses is not trivial in many actual scenarios: a memory chip may require multiple row accesses, for example, in order to perform a mis-aligned read. In addition, FPGA synthesis is substantially simpler when mis-aligned addresses are not permitted.

Importing and Exporting Memory Contents

Pins (assuming "Classic Logisim" appearance)

A on west edge (input, bit width matches Address Bit Width property)

Selects which of the values in memory is currently being accessed by the circuit. In 'Dual' and 'Quad' line mode, the address A must be a multiple of 2 or 4, respectively, and two or four consecutive addresses are accessed starting at address A.

D on west edge (input, bit width matches Data Bit Width property)

This input is present only if "separate data buses" is selected for the Databus implementation property. When a store is requested (via the clock changing from 0 to 1 while S is 1 and S0 if present is also 1), the value found at this port is stored into memory at the currently selected address.

1 on west edge (input, bit width matches Data Bit Width property)

This input is present only if "Dual" or "Quad" line mode is selected and "separate data buses" is selected for the Databus implementation property. When a store is requested (via the clock changing from 0 to 1 while S1 is 1), the value found at port 1is stored into memory at A+1, i.e. 1 location beyond the currently selected address.

2 and 3 on west edge (inputs, bit width matches Data Bit Width property)

These inputs are present only if "Quad" line mode is selected and "separate data buses" is selected for the Databus implementation property. They behave similarly to the 1 input, but using control signals S2 and S3, respectively, and addresses A+2 and A+3, respectively.

D on east edge (input/output or output, bit width matches Data Bit Width property)

If L is 1 or floating (or if the L input is not present), then the RAM component emits the value found at the currently selected address on this port, unless the address is mis-aligned in which case an error (E) value is emitted instead. If there is a single bidirectional load/store port, the value read from this port is stored whenever a store is requested.

1, 2, 3 on east edge (inputs/outputs or outputs, bit width matches Data Bit Width property)

These ports are present only if "Dual" or "Quad" line mode is selected. They each behave similarl to the D input/output or output port, but using addresses A+1, A+2, and A+3, respectively.

S on west edge (input, bit width 1)

Store: When it is 1, a clock pulse will result in storing data into memory at the current selected address(es).

S0, S1, S2, and S3 on west edge (inputs, bit width 1)

Store i: Only present in "Dual" or "Quad" line modes, these individually control the store behavior for each of the selected lines. Address A+i is only written when both S and Si are 1.

triangle on west edge (input, bit width 1)

Clock input: Controls the timing of store requests. When S is 1, and the clock input rises from 0 to 1 (or is triggered according to the 'Trigger' property) while S is 1 (and some of the Si inputs, if present, are also 1), then the value at the data input bus(es) is immediately written into the currently selected address. Note that the clock has no effect on load actions: loads happen asynchronously and continously, regardless of the clock triggers.

L on west edge (input, bit width 1)

Load: This port is only present if there bidirectional load/store ports are used. When L=1, the bidirectional data port or ports are set to output mode, and the value at the current selected address(es) are output to those data ports.

Properties

When the component is selected or being added, the digits '0' through '9' alter its Address Bit Width property and Alt-0 through Alt-9 alter its Data Bit Width property.

Address Bit Width

The bit width of the address bits. The number of values stored in RAM is 2^addrBitWidth.

Data Bit Width

The bit width of each individual value in memory.

Line Size

Allows for Single, Dual, or Quad line mode.

Trigger

Configures how the clock input is interpreted. This only affects store operations. When a store operation is selected via the S and Si inputs, the value rising edge indicates that the memory should store values at the instant when the clock rises from 0 to 1. The falling edge value indicates that it should update at the instant the clock falls from 1 to 0. The high level value indicates that the memory should update continuously whenever the clock input is 1. And the low level value indicates that it should update continuously when the clock input is 0.

Memory Type

If set to 'Volatile' the memory contents will be lost when the simulation is reset or when Logisim exits. In addition, FPGA synthesis will initialize volatile memory to all zeros. If set to 'Non-Volatile', the memory contents will be retained even when the simulation is reset or when Logisim exits, and FPGA synthesis will use the current contents of the memory at the time sythesis occurs to initialize the FPGA memory.

Databus implementation

Configures which of the two styles of data interface is used for communicating data into and out of the RAM.

Label

The text within the label associated with the register.

Label Font

The font with which to render the label.

Appearance

Selects between the "Classic Logisim" appearance style, which is somewhat more compact, or "ANSI" style, which is more conventional but larger.

Poke Tool Behavior

Clicking the RAM component brings keyboard and mouse focus to the RAM (indicated by a red rectangle), allowing for the contents to be viewed or edited. Because Poke Tool editing all takes place within a very small space, the interface for this is severely but necessarily constrained. For all but the simplest editing, it is more convenient to right-click the RAM and select "Edit Contents..." to bring up the integrated hex editor.

The Poke Tool has two modes of operation: You can edit the address displayed, and you can edit an individual value at some memory location.

Editing Addresses: Use the Poke Tool and click anywhere within the memory component but outside the gray box holding the memory contents. Logisim will draw a red rectangle around the address at the upper left corner. From here:

• Typing R or r will clear the contents of memory.

• Typing hex digits will change the address (assuming the new address isn't too large) and scroll the memory contents to show that address.

• Scrolling with the mouse wheel increments or decrements the address and scrolls the memory forward or backward.

• The Down (or Enter) key will increment the address and scroll the memory contents forward by one row.

• The Up (or Backspace or Delete) keys will also increment or decrement the address to key will decrement the address and scroll the memory contents backwards by one row.

• The Page Down (or Space) and Page Up keys will increment or decrement the address to scroll the memory contents forward or backward by one full page.

Editing Contents: Use the Poke Tool and click anywhere within the memory component within the gray box holding the memory contents. Logisim will draw a red rectangle around the memory cell currently being edited. From here:

• Typing R or r will clear the contents of memory.

• Typing hex digits will change the contents of that cell.

• Scrolling with the mouse wheel moves up or down to an adjacent memory cell.

• The Up, Down, Left, and Right arrow keys move to an adjacent memory cell.

• The Page Up and Page Down keys move up or down by a full page.

• The Backspace (or Delete) and Tab (or Space) keys similarly move to the previous or next memory cell.

Menu Tool Behavior

Right-clicking the RAM component brings up several actions in a context menu:

• Edit Contents...: Brings up the integrated hex editor to view and edit the entire memory contents in a separate window

• Clear Contents: Resets all values in memory to all zeros.

• Load Memory Image...: Loads entirely new memory contents by importing from a file. A variety of file formats are supported: see Memory Import/Export Format in the User's Guide for details.

• Save Memory Image...: Saves the entire contents of memory to an external file. A variety of file formats are supported: see Memory Import/Export Format in the User's Guide for details.

FPGA Synthesis

Supports VHDL synthesis. Only rising and falling edge triggers are supported. Non-Volatile memory is only supported on Altera devices. Only the "separate data bus" interface option is supported for synthesis.

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