Random

Library:	Memory
Introduced:	2.3.0
Appearance:	Classic Logisim: ANSI:

Behavior

This component iterates through a pseudorandom sequence of numbers, which steps forward to the following number in the sequence each time the clock is triggered while the component is enabled. Technically speaking, the algorithm used to compute the pseudorandom sequence is a linear congruential generator: Starting from a seed r₀, the following number r₁ is the number

The next value r₂ is computed from r₁ using the same computation, and so forth. This sequence is of 48-bit numbers; the value seen from the component is the low-order bits as configured by its Data Bits property, after first throwing out the lower 12 bits of the current seed.

Besides the clock input, the component also includes an enable input, which leads the clock input to be ignored when enable is 0, and the reset input, which resets the component's value asynchronously to the initial seed r₀.

The initial seed is user-configurable. If it is configured at 0 (which is the default), then the seed is based on the current time; when instructed to reset through the reset input, the component computes a new seed based on the new current time.

Pins (assuming "Classic Logisim" appearance)

East edge, labeled Q (output, bit width matches Data Bits property)

Outputs the value currently stored by the component.

West edge, top pin, labeled with a triangle (input, bit width 1)

Clock: At the instant that this is triggered as specified by the Trigger property, the component steps to the following number in its sequence.

West edge, bottom pin (input, bit width 1)

Enable: The component is enabled when this input is disconnected or 1; but if it is 0, then the clock input is ignored.

South edge (input, bit width 1)

Reset: When this is 1, the pseudorandom sequence asynchronously resets to the initial seed. (If seed is 0, this new seed should be different from the initial seed used previously.)

Properties

When the component is selected or being added, Alt-0 through Alt-9 alter its Data Bits property.

Data Bits

The bit width of the value emitted by the component.

Seed

The starting value used for the pseudorandom sequence. If this is 0 (the default), then the starting value is based on the time that the random sequence began.

Trigger

Configures how the clock input is interpreted. The value rising edge indicates that the component should update its value at the instant when the clock rises from 0 to 1. The falling edge value indicates that it should update at the instant the clock falls from 1 to 0.

Label

The text within the label associated with the component.

Label Font

The font with which to render the label.

Label Location

The relative direction in which to render the label.

Show in Registers Tab

Whether the value of the register should appear in the "State" tab at the bottom left of the canvas, which can be useful for seeing all of the state values contained in a circuit at a glance.

Appearance

Selects between the "Classic Logisim" appearance style, which is somewhat more compact, or "ANSI" style, which is more conventional but larger.

Poke Tool Behavior

When using "Classic Logisim" appearnce, clicking within the component will generate a new random number, advancing the value stored by one step in the sequence of random numbers. Pressing Backspace or Delete will reset the state using the initial seed.

FPGA Synthesis

Supports VHDL and Verilog synthesis.

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