Multiplexer

Library:	Plexers
Introduced:	2.0 Beta 11
Appearance:

Behavior

Copies an input on the west edge to the output on the east edge; which of the inputs to copy is specified via the current value received through the select input on the south edge. I find it useful to think of a multiplexer as analogous to a railroad switch, controlled by the select input.

Note: some authorities spell this multiplexor, but multiplexer is the predominant spelling.

Pins (assuming component faces east, select is bottom/left)

West edge, variable number (inputs, bit width matches Data Bits property)

Data values, one of which is to be routed to the output. Each input data value is numbered, starting with 0 on the north.

East edge (output, bit width matches Data Bits property)

The output value will match the input values on the west edge whose number is the same as the value currently received through the select input on the south. If the select input contains any unspecified (i.e., floating) bits, then the output is completely floating.

South edge, left side indicated by gray circle (input, bit width matches Select Bits property)

Select input: The value of this input determines which input on the west edge to route to the output on the east edge.

South edge, right side (input, bit width 1)

Enable (optional): When 0, the multiplexer's output consists of all floating bits, regardless of the data and select inputs.

Properties

When the component is selected or being added, the digits '1' through '4' alter its Select Bits property, Alt-0 through Alt-9 alter its Data Bits property, and the arrow keys alter its Facing property.

Facing

The direction of the component (its output relative to its input).

Select Location

The location of the select and enable lines relative to the component.

Select Bits

The bit width of the component's select input on its south edge. The number of inputs to the multiplexer will be 2^selectBits.

Data Bits

The bit width of the data being routed through the multiplexer.

Disabled Output

Specifies what each bit of the output should be when the component is disabled (i.e., when the enable pin is 0). Options include zero and floating; in the latter case, when disabled, the output is effectively disconnected from any other ports.

Include Enable?

Whether the component should have an enable input.

Poke Tool Behavior

None.

FPGA Synthesis

Supports VHDL and Verilog synthesis.

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