Port I/O

Library: Input/Output
Introduced: 2.1.3
Appearance:

Behavior

This component was designed for FPGA synthesis, but it may be useful as a generic I/O component as well. A Port I/O component displays a series of values as small colored boxes: 0 is shown as dark green, 1 as bright green, X (floating) as gray, and Z (error) as red. The component can be configured as an output, as an input, or as a bi-directional port:

In output mode, this component is mostly equivalent to a simple array of LED components or a LED Matrix, or in some cases could be replaced by an Output Pin. In input mode, a Port I/O component is mostly equivalent to a DIP Switch, or in some cases could be replaced by an Input Pin. However, Port I/O has certain advantages: it supports up to 120 bits, it is very compact, it supports a bi-directional mode, and it supports FPGA synthesis. In particular, it is the only way from within Logisim to make use of the bi-directional features of FPGA I/O resources.

Pins

When configured in bi-directional or output mode, there is one data input pin (or, if there are more than 32 bits, enough data input pins as needed for all of the bits). The values at this port (or ports) are used to drive the lights.

When configured in bi-directional or input mode, there is one data output pin (or, if there are more than 32 bits, enough data output pins as needed for all of the bits). Te values at this port (or ports) are driven depending on the user-selected toggle switches.

When configured in the bi-directional 'in/out (single enable)' mode, there is a single 1-bit control input that determines whether all of the bits are in output mode (when the control input is a 1) or input mode.

When configured in the bi-directional 'in/out (per-bit enable)' mode, there is one n-bit control input for each n-bit data input. Each of these control bits determines whether the corresponding data bit is in output mode (when the control input is a 1) or input mode.

Properties

When the component is selected or being added, Alt-0 through Alt-9 alter its Number of PIN property, and the arrow keys alter its Facing property,

Facing
The location of the ports relative to the component.
Label
The text within the label associated with the component.
Label Location
The location of the label relative to the component.
Label Font
The font with which to render the label.
Label Color
The color with which to draw the label.
Number of PIN
The number of bits for the component, up to a maximum of 128.
Direction
Whether the Port I/O should function in input mode, output mode, in/out (single enable) mode, or in/out (per-bit enable) mode.

Poke Tool Behavior

For bits in input mode, pressing the mouse on a colored square will cycle through the values 0 (light green), 1 (dark green), and X (floating, gray).

FPGA Synthesis

Supports VHDL and Verilog synthesis.

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